1. Field of the Invention
The invention relates to a method for producing a gate on a semiconductor substrate, and more particularly, to a method for producing a gate that will prevent bulging sidewalls of the gate produced by an annealing process.
2. Description of the Prior Art
Manufacturing a semiconductor IC comprises many process, such as the mask and photolithography process, coating, etching, and deposition. The progress of science and technology has led to high density of an IC in semiconductor manufacturing such that more transistors have to be set in a curtain area. For example, a silicon substrate with an area of 1-2 cm2 may contain hundreds of thousands transistors. In order to avoid interference between transistors or short circuits, much research and design is needed to improve the above-mentioned processes of manufacturing a semiconductor. In addition, when manufacturing a transistor, the quality of the gate dielectric layer is a key point of the yield. A gate dielectric layer with bad quality is easily susceptible to breakdown and reduces the lifetime of a transistor. Therefore, improving the quality of a gate dielectric layer is an important issue.
The manufacturing method according to the prior art is illustrated below. Please refer to FIGS. 1-4, which are schematic diagrams of the formation of a gate on a semiconductor chip 10 according to the prior art. As shown in FIG. 1, an oxide layer 14 is formed on the silicon substrate 12 of the semiconductor chip 10 for serving as a dielectric layer of the gate. Then a doped polysilicon layer 16 and a silicide layer 18, for example, a WSix layer, are formed sequentially on the oxide layer 14, wherein the doped polysilicon layer 16 is used for being a main conductive layer of the gate, and the silicide layer 18 is used for reducing resistance. After that, a mask layer 20 comprising silicon nitride (SixNy) is formed on the surface of the silicide layer 18, and finally a photoresist layer 22 is formed on the mask layer 20.
Please refer to FIG. 2. A lithography process is then performed to define a pattern of the gate on the photoresist layer 22. After the lithography process, an anisotropic etching process, such as a dry-etching process, is performed to remove a portion of the mask layer 20 not covered by the photoresist layer 22 so as to transfer the pattern of the photoresist layer 22 to the mask layer 20. Then the remaining mask layer 20 is taken as a hard mask to etch the silicide layer 18 and the doped polysilicon layer 16, thereby forming the gate 24 and gate 26.
As shown in FIG. 3, the oxide layer 14 serves as a pad oxide layer for performing a first ion implantation process to form a plurality of doped areas (not illustrated) in the silicon substrate 12. Then a first annealing process is performed to activate the ions in the doped areas resulting in a plurality of lightly doped drains(LDD) 28 beside the gates 24 and 26. After that, a silicon nitride deposition is performed on the semiconductor chip 10 and an anisotropic etching process is performed to etch back portions of the silicon nitride sequentially to form a plurality of spacers 30 on the sidewalls of the gates 24 and 26, as shown in FIG. 4. Finally, a second ion implantation and a second annealing process are performed to form the source and drain 32 beside the gates 24 and 26. Therefore manufacturing of an MOS transistor is finished.
However, when performing the first and the second annealing process according to prior art, the suicide layer 18 in the gates 24 and 26 often becomes a bulging shape because of thermal expansion (please refer to FIG. 3). Thus the following silicon nitride layer will deposit along the bulging sidewalls of the silicide layer 18, resulting in the bulging spacers 30. As illustrated in FIG. 4, the distance between the gate 24 and the gate 26 is reduced because of the bulging shape of the gates 24 and 26. The reduced distance will influence the following processes of manufacturing the semiconductor chip. For example, when forming a contact plug between the gates 24 and 26, the dielectric material layer and conductive material layer later depositing between the gate 24 and gate 26 easily form an over hang, further resulting in more serious problems of shapeless covers, such as a void or a seam. In addition, the bulging shape of the gates 24 and 26 will also make the spacer 30 being over etched, possibly causing a short circuit between the gate and the contact plug.
Furthermore, a micro-loading effect easily occurs when using the dry etching to define the pattern of the gate 24, 26 on the semiconductor chip 10, which reduces the symmetry of etching. For example, to form a symmetric sidewall of a gate is difficult both in a dense region or an isolation region, as well as to control the line width accurately. Therefore, to eliminate the above problem is also a serious issue.
Consequently, there is a strong need to provide a semiconductor chip with a high integration while simultaneously avoiding the short distance between the gates resulting from bulging shapes of the spacers and the asymmetry caused by the dry etching.
It is therefore a primary objective of the claimed invention to provide a method for producing a gate on a semiconductor substrate to solve the above-mentioned problem.
According to the claimed invention, the claimed invention provides a method for producing a gate on a semiconductor substrate, wherein the semiconductor substratecomprises a first oxide layer, a conductive layer, a silicide layer, and a hard mask. The method comprises defining a pattern of the gate on the hard mask, performing an etching process to remove portions of the silicide layer and the conductive layer which are not covered by the hard mask, performing an O2 flush process to form a second oxide layer on the surface of the first oxide layer, and performing a wet etching process to remove a portion of the silicide layer to give sidewalls of the silicide layer a concave shape and to etch back the second oxide layer.
It is an advantage of the claimed invention that an O2 flush process is performed to raise the total thickness of the oxide layer before the wet etching, so that the thickness of remaining oxide layer after the wet etching is still great enough for being a pad oxide layer for protecting the semiconductor substrate from the ion implantation process even though the wet etching will remove portions of the oxide layer. Furthermore, because the claimed invention gives the both sidewalls of the silicide layer a concave shape, the gate will still have an approximately vertical structure even though the silicide layer undergoes thermal expansion during the annealing process. Therefore the above-mentioned problem resulting from the bulging shape of the gate will be effectively avoided.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.